News
Website Migration - 02.03.2018
We have moved to new address:
Check it out for news about project and the group activity!
FPGA Weekly Meetings - W V - 09.01.2018
This Tuesday:
- We'll have a tutorial for beginners on finite state machines.
- Bartosz Dziedzic will present the subject of Dynamic Reconfiguration
- We'll discuss projects/problems/ideas
Digilent Design Contest - Qualified! - 08.01.2017
We have just received an information that our young team has been qualified to Digilent Design Contest!
They will develop a demonstration of a simple Augmented Reality device on Zybo platform.
FPGA Weekly Meetings - WIV - 19.12.2017
This Tuesday:
- We'll have a tutorial for beginners on components instantiation, IP Cores and more.
- We'll discuss projects/problems/ideas
ZCU102 Has Arrived! - 01.12.2017
Great news! We have just received the powerful ZynqMPSOC powered board.
The module will replace in the future the current JPET Controller and enable much more advanced real-time processing.
FPGA Weekly Meetings - WIII - 21.11.2017
This Tuesday:
- Karol Farbaniec will present his implementation of TDC on Lattice FPGA and discuss time measurement issues
- We'll discuss projects/problems/ideas
Additionally a tutorial for FPGA/VHDL beginners will be held at 15:00
grzegorz.korcyl (at) uj.edu.pl
Real-time Video Processing - 20.11.2017
This Monday we had a really successful workshop on video processing on Zybo Z7 boards.
The workshop was prepared by the experts from Kamami.pl and Digilent. 20 participants have learned video processing techniques, Vivado and HLS.
We are looking forward more such workshops to come in the future!
grzegorz.korcyl (at) uj.edu.pl
FPGA Weekly Meetings - WII - 06.11.2017
This Tuesday:
- Bartłomiej Flak will present his work on control and monitoring system developed for JPET
- Krzysztof Nowakowski will present a short introduction to Pynq platform and Python on FPGAs
- We'll discuss projects/problems/ideas
grzegorz.korcyl (at) uj.edu.pl
Real-time Video Processing with KAMAMI and Digilent - 04.11.2017
On Monday 20th November 2017, we'll be hosting a free of charge workshop on video processing on Zynq devices, organized by KAMAMI and Digilent.Head out to [this] link and register!
grzegorz.korcyl (at) uj.edu.pl
First 3D reconstruction - 24.10.2017
Enhanced image reconstruction, including 3D and TOF functionalities has been successfully implemented entirely in the FPGA!
In programmable logic, we are finding LOR candidates and reconstruct the annihilation point coordinates. Then, only X, Y, Z values are being sent from the JPET Controller to the server that produces 3D canvas with the scanner visualization.
You can find a video showing it in action under [this] link.
grzegorz.korcyl (at) uj.edu.pl
FPGA Weekly Meetings - Reboot after summer - 18.10.2017
After intensive summer season, we are resuming our weekly meetings!
On Tuesday 24th October we will meet, hopefully in a growing group and discuss about current and future projects, activities, perspectives and ideas.
This time we team up with Students Scientific Association of Robotics and Artificial Intelligence at Faculty of Mathematics and Informatics of Jagiellonian University.
grzegorz.korcyl (at) uj.edu.pl
END OF FPGA SUMMER INTERNSHIPS - 14.08.2017
First FPGA Summer Camp has ended last Friday. We had an entire month of coding, debugging, discussing and doing research. Once again thanks to all participants!
Here are some stats:
- 16 people have registered
- About 10 people attended each day
- We did projects concerning: video processing, algorithmics in HLS, neural networks and high speed networking, PS-PL communication on Zynq
- We survived temperatures 37+ degrees
- Only 4 pizzas were eaten
grzegorz.korcyl (at) uj.edu.pl
FPGA SUMMER INTERNSHIPS - 13.06.2017
Do you have some free time during holidays and would like to check out how FPGAs work?
That's great because we announce the summer internships!
From July 17th to August 11th at the Faculty of Physic, Astronomy and Applied Computer Science you can learn about the basics, try to develop some projects and run it on hardware. If you have some ideas but don't have the hardware or experience you are also welcome.
Start by sending an email to grzegorz.korcyl (at) uj.edu.pl
grzegorz.korcyl (at) uj.edu.pl
Real-time image reconstruction at conferences - 12.06.2017
Implementation of image reconstruction from tomographic data has been presented for the first time to external experts in tomography at two conferences. First one was XL IEEE-SPIE Joint Symposium Wilga 2017 and the second one was 2nd Jagiellonian Symposium on Fundamental and Subatomic Physics
The project received much interest from the experts from USA universities and was reviewed as having much potential in development of true innovative solutions, not existing on market so far.
grzegorz.korcyl (at) uj.edu.pl
FPGA Weekly Meetings 2017 W2 - 23.05.2017
This Tuesday, May 23rd, Paweł Strzempek will present his latest project: readout system designed for Digital JPET based on Virtex Ultrascale boards and AXI components.
grzegorz.korcyl (at) uj.edu.pl
Real time image reconstruction - 08.05.2017
Another step into tomographic image reconstruction in real time has been made!
JPET Controller allows to process data from 8 TRBv3s in several steps leading to image creation:
- Receive and synchronize data units from the TRBv3s
- Hit data extraction
- Detector geometry mapping
- Coincidence search
- LOR coordinates calculation
- Data transmission
All those steps, performed 50 000 times per second, processing hundreds MB per second reduce the data volume to hundreds of KB and limit the processing on the CPU only to drawing points. All this on a single Xilinx Zynq.
Next steps are:
- Introduction of calibration parameters
- Time-Of-Flight
- 3rd dimension Z-Axis
Under this [link] you can find a video that shows reconstructed image being drawn in real time as the radioactive source on robotic arm scans the detector.
grzegorz.korcyl (at) uj.edu.pl
Paweł Strzempek doctoral defense - 26.04.2017
Congratulations to dr. Paweł Strzempek for defending with distinction! his PhD thesis "Development and evaluation of a signal analysis and a readout system of straw tube detectors for the PANDA spectrometer".
You can find his work under this [link]
grzegorz.korcyl (at) uj.edu.pl
Meeting with Digilent and Kamami - 20.03.2017
Today we had a meeting with representants from Digilent and Kamami. After presenting our hardware related activities at Jagiellonian Univeristy we have discussed potential fields for cooperation. Many thanks go to Piotr Warchoł and Karol Farbaniec for participating and presenting Garage of Complexity and Robotics and Artificial Intelligence Students Association.
grzegorz.korcyl (at) uj.edu.pl
FPGA Weekly Meetings 2017 W1 - 14.03.2017
This Tuesday, March 14th, we will review the activities in students science clubs in order to prepare for meeting with representants from Kamami and Digilent.
grzegorz.korcyl (at) uj.edu.pl
Medical Image Reconstruction - 03.03.2017
First images have been produced by JPET Controller board!
The controller processes data streams from 8 TRBs, parses the TDC data and recovers hits on scintillators. The hits are correlated together by scanning with a time window and then mapped into the detector geometry in order to recover LOR coordinates. Finally instead of raw TDC data only two points from LOR are being sent.
grzegorz.korcyl (at) uj.edu.pl
Engineering Thesis Defenses - 19.01.2017
Recently two of our colleagues have defended their thesis based on research involving FPGAs.
The first one: "Particle track recognition on FPGA devices", by Emilia Pieczonka and
The second one: "Particle track reconstruction on FPGA devices" by Kuba Cierlik
They both are from Faculty of Electrical Engineering, Automatics, Computer Science and Biomedical Engineering from University of Science and Technology.
Congratulations!
grzegorz.korcyl (at) uj.edu.pl
FPGA Weekly Meetings 2016 W7 - 18.12.2016
This Tuesday, December 20th, we will review some techniques used in simulations.
grzegorz.korcyl (at) uj.edu.pl
II Symposium on FPGAs - 18.12.2016
Last week, Friday 9th, we had a very successful symposium on FPGAs. It was the second edition of the event started in 2015.
This the day was fill with interesting content. We started with an excursion to Solaris synchrotron and then moved to FAIS for 2 sessions that lasted up to almost 21:00!
Here's a short summary in numbers:
- 65 people attended the event
- 35 people visited Solaris
- 13 talks were given
- 8 viewers connected online through twitch.tv
- 700 tiny sandwiches were eaten throughout the day
I believe next year we can do even better!
grzegorz.korcyl (at) uj.edu.pl
FPGA Weekly Meetings 2016 W6 - 21.11.2016
This Tuesday, November 22nd, Karol Farbaniec will present a tutorial on DSP blocks in Zynq devices.
grzegorz.korcyl (at) uj.edu.pl
VCU108 have arrived! - 14.11.2016
We have just received brand new VCU108 Evaluation Boards with Xilinx Virtex Ultrascale XCVU095. Those powerful platforms will be used in the readout of silicon photomultipliers layer for JPET tomograph.
grzegorz.korcyl (at) uj.edu.pl
II FPGA Symposium - Update - 10.11.2016
Quick updates on the organization of the II FPGA Symposium:
- Symposium date is the 9th of December 2016, presentations will start from 12:30
- Prof. Tadeusz Łuba from Politechnika Warszawska will give a special talk on the importance on logic synthesis
- Dr Ludovico Minati will present his projets including FPGAs and FPAAs (Field Programmable Analog Arrays)
- There is a chance to visit Narodowe Centrum Promieniowania Synchrotronowego SOLARIS
Please register on
http://grzegorzkorcyl.wixsite.com/sympozjumfpga2016
Deadline is November the 18th!
grzegorz.korcyl (at) uj.edu.pl
FPGA Weekly Meetings 2016 W5 - 10.11.2016
Next Tuesday, November 15th, Bartosz Dziedzic will introduce how Emacs can speed up VHDL code development and we'll see how to debug our designs using Integrated Logic Analyzer in Vivado.
grzegorz.korcyl (at) uj.edu.pl
FPGA Weekly Meetings 2016 W4 - 04.11.2016
Next Tuesday, November 8th we will review the project management tools like integration of custom code editors and repositories with Vivado.
grzegorz.korcyl (at) uj.edu.pl
FPGA Weekly Meetings 2016 W3 - 24.10.2016
This week Grzegorz Połeć will give a tutorial on logic components and PetaLinux communication.
grzegorz.korcyl (at) uj.edu.pl
ZC706 Arrived - 24.10.2016
Brand new Zynq7000 All Programmable SoC ZC706 Evaluation Kit has just arrived!
It's a powerful set for development of various projects, mainly engaging embedded processor.
Together with SDSoC it opens a new direction for exploring various mechanisms of data processing.
grzegorz.korcyl (at) uj.edu.pl
SDSoC License Pack Received! - 19.10.2016
We have just received a pack of 25 licenses for SDSoC Software from Xilinx!
It gives us a great chance to explore high-end technology and getting the most out of our hardware. Especially when a powerful Zynq Z706 board is arriving soon to our hardware library!
grzegorz.korcyl (at) uj.edu.pl
FPGA Weekly Meetings 2016 W2 - 17.10.2016
This week we'll have a closer look at common timing issues in FPGA designs and timing constraints.
grzegorz.korcyl (at) uj.edu.pl
FPGA Weekly Meetings 2016 W1 - 11.10.2016
Holiday season is over so we are restarting with weekly meetings of the FPGA group.
We'll try to meet regularly on Tuesdays at 16:00 in B-2-50 seminar room.
This week we'll review our projects after the holidays and welcome new members.
If you would like to join the meetings, just send me an email and I'll include you in the mailing list to receive notifications about incoming meetings and topics.
grzegorz.korcyl (at) uj.edu.pl
II Symposium on FPGAs 2016 - 11.10.2016
It's my pleasure to announce that the registration for II Cracow Symposium on FPGAs it now open!
Go to http://grzegorzkorcyl.wixsite.com/sympozjumfpga2016 to see more details and register
grzegorz.korcyl (at) uj.edu.pl
IEEE Real Time Conference 2016 - 06.06.2016
Our system for data acquisition from tracking detectors, based on TRBv3 platform has been presented at IEEE Real Time Conference 2016 in Padova.
It is worth to mention that the TRBv3 platform itself found it place on several other contributions at that conference!
grzegorz.korcyl (at) uj.edu.pl
Advanced hardware from ALTERA - 30.05.2016
More hardware to explore! We have been just granted DE1-SoC and DE5 development kits from ALTERA by their university program.
- DE1-SoC is a Cyclone V based paltform:
- DE5 is an advanced Stratix V platform:
grzegorz.korcyl (at) uj.edu.pl
SIGASI is partnering up - 24.05.2016
Great HDL development IDE SIGASI has just provided a couple of licenses for our group. Their advanced, Eclipse-based software is a significant support in the logic development mostly thanks to real-time syntax check and code decomposition that provides auto-completition, something so much appreciated when writing in VHDL ;)
grzegorz.korcyl (at) uj.edu.pl
Founding for hardware received! - 19.05.2016
Great news! We have received additional founding from the faculty in the program DSC2016.
It is a clear sign that our effort in propagating FPGA technology as an important branch in Computer Science and Experimental Physics related projects has been noticed and appreciated.
Here's what we'll buy in the near future:
- Advanced Zynq-based development kit ZC706
- Two basic, Artix-based development kits Arty
- 10GbE Network equipment
grzegorz.korcyl (at) uj.edu.pl
A gift from ALTERA - 11.05.2016
Thanks to ALTERA for supporting us by donating a set of licenses for their Quartus design tools. We are awaiting development boards and hardware as well.
grzegorz.korcyl (at) uj.edu.pl
PANDA Forward Tracker successfull beamtime - 05.06.2016
On Monday 2nd of May 2016 we have finished a successfull, two-week beamtime in Forschungszentrum Juelich GmbH for our prototype of Forward Tracker constructed for PANDA (FAIR, Germany).
Great amount of work was needed in order to condition the detector and also for the design and evaluation of its FPGA-based readout system.
The use of TRBv3 hardware together with the software environment for data processing, resulted in very smooth data collection and achievement of low-noise, high-resolution results.
For more details about the readout system, please check out the link:
http://www.doit.fais.uj.edu.pl/fpga-trbv3-platform
grzegorz.korcyl (at) uj.edu.pl, pawel.strzempek (at) uj.edu.pl
JPET Controller power up! - 07.04.2016
After several ups and downs we have successfully evaluated all the key elements of the JPET Controller and the hardware is ready to use!
In just short time several test projects have been run, including mainly:
- IBERT (Integrated Bit Error RatioTester) on all the 16x optical links
- ZYNQ Processing Systems with DDR3 and UART-USB
- Gigabit Ethernet Module on all the 16x optical links
Now everything is ready to start implementing tomographic data processing!
For more details about the system, please check out this link:
http://www.doit.fais.uj.edu.pl/fpga-jpet-data-analysis
grzegorz.korcyl (at) uj.edu.pl
XCell and XCell Software Journals available - 01.04.2016
Both journals are now available for you to check out in selected seminar rooms. Latest releases will keep coming in.
According to the publisher:
Xcell Journal offers a wealth of practical engineering knowledge and in-depth coverage of the latest applications and technologies.
Xcell Software Journal offers a wealth of practical knowledge and in-depth coverage of the latest applications and methods for software and system design.
Take a look and enjoy!
grzegorz.korcyl (at) uj.edu.pl
JPET DAQ System up and running - 25.03.2016
A large FPGA-based Data Acquisition Systems for JPET tomograph prototype is up and running!
The system consists of 9x TRBv3 modules running in 1x Master - 8x Slaves mode, collecting data from 384 photomultipliers, delivering signals to 1536 high-resolution TDC channels.
Generated data stream is forwarded into 3x 1Gb network interfaces of a server class rack computer. We are awaiting for the founds dedicated to network upgrade to 10Gb solutions.
Great hardware and software solutions allow to display data quality histograms constructed in the real time as well as storing data for further offline processing.
For more details about the readout system, please check out the link:
http://www.doit.fais.uj.edu.pl/fpga-trbv3-platform
grzegorz.korcyl (at) uj.edu.pl
Xilinx Donation - 05.03.2016
I'm glad to announce that we have managed to acquire a generous donation for Xilinx Inc.
The entire package contains:
- 2x ZedBoard development kit
- 25x Vivado HLx: System Edition license
Looking forward further fruitful cooperation!
grzegorz.korcyl (at) uj.edu.pl
FPGA Group Meetings - 01.02.2016
With the new semester we start weekly meetings dedicated to FPGA technology. It's a great place to discuss, consult and learn about various aspects of logic development.
The meetings take place in G-1-08 each Tuesday at 16:00.
Everybody is welcome to come!
grzegorz.korcyl (at) uj.edu.pl
New TRBv3 application: mobile PET/MRI - 10.01.2016
Yet another application of the TRBv3 Data Acquisition System!
We are currently working on introducing the platform for the readout of Multi-Pixel Photon Counters (MPPC) used in the prototpe of the PET insert developed for simultaneous PET/MR imaging of human body.
The project is carried out at FAIS by dr Marcin Zieliński who acquired a grant in LIDER project from NCBR.
Check out the link for more information:
http://lider.koza.if.uj.edu.pl/
grzegorz.korcyl (at) uj.edu.pl